1. Technical Field
The present invention relates to a shift register that can transfer a pulse, to a method of controlling the same, to an electro-optical device, and to an electronic apparatus.
2. Related Art
Electro-optical devices, which perform display through an electro-optical change of an electro-optical material, such as liquid crystal, or organic electroluminescence (EL), have been widely used as display devices such as an information processing apparatus, a television, or the like. Among the electro-optical devices, there is an active-matrix-type device which drives a pixel through a pixel switch. That is, in the active-matrix-type electro-optical device, pixel electrodes are formed so as to correspond to intersections of scanning lines extending in a row direction and data lines extending in a column direction. In addition, a pixel switch, such as a thin film transistor or the like, which is turned on or off according to a scanning signal supplied to the scanning line, is inserted between each pixel electrode and each data line at the intersection. In addition, a counter electrode is provided so as to face the pixel electrode with the electro-optical material therebetween.
In this configuration, if a scanning signal of an ON voltage is applied to the scanning line, a pixel switch connected to the corresponding scanning line is turned on. At the time when the pixel switch is turned on, if a data signal according to a gray-scale level (concentration) is supplied to the data line, since the corresponding data signal is applied to the pixel electrode through the pixel switch, a voltage according to the data signal is applied to the electro-optical material interposed between the corresponding pixel electrode and the counter electrode. Thereby, the electro-optical material is subjected to an electro-optical change. As a result, in each pixel, an amount of transmitted light, an amount of reflected light, or an amount of emitted light (at least, an amount of light which an observer can recognize) depends on the voltage of the data signal applied to the pixel electrode. Therefore, this control is performed for every pixel, which results in predetermined display.
Here, the scanning signal is output from a scanning line driving circuit. The scanning line driving circuit has a Y shift register in which a plurality of stages of circuit blocks are connected with multiple stages in a Y direction. The Y shift register shifts a start pulse supplied at the beginning of a vertical scanning period using a Y clock signal that becomes a reference of the horizontal scanning. In addition, the data signal is output from the data line driving circuit. The data line driving circuit supplies the sampling signal to a sampling switch sampling the image signal supplied in synchronization with the vertical scanning and the horizontal scanning for every data line for a horizontal effective scanning period. In more detail, the data line driving circuit has an X shift register in which a plurality of stages of circuit blocks are connected with multiple stages in an X direction. The X shift register shifts a start pulse supplied at the beginning of a first horizontal scanning period using an X clock signal in synchronization with a period for which the image signal is supplied.
In JP-A-2003-228315, as the shift register used in the above-mentioned driving circuits, a shift register is disclosed in which a plurality of circuit blocks are cascade-connected and each of the circuit blocks has a transfer circuit and a clock control circuit. Here, the transfer circuit is supplied with first and second clock signals, but if periods for which these signals become effective overlap, there is a possibility that erroneous operation occurs. Accordingly, a structure using a waveform shaping circuit shown in FIG. 27 is disclosed in JP-A-2003-228315. This waveform shaping circuit is composed of five inverters 711 to 715. The inverters 714 and 715 constitute a latch circuit. Thereby, the overlapping period can be decreased.
However, in the waveform shaping circuit disclosed in JP-A-2003-228315, in order to arrange phases of a non-inverted clock signal CL and an inverted clock signal CL*, it is required to use the inverters 712 to 715 each having a high driving capability. For this reason, there is a problem in that power consumption and noise increase. In addition, if the inverters 712 and 715 each having a low driving capability are used, waveforms of the non-inverted clock signal CL and the inverted clock signal CL* overlap, which results in erroneous operation in the transfer unit circuit. In particular, when the pulse is transferred from any transfer unit circuit to the next transfer unit circuit, a problem occurs in that the pulse is transferred from the next transfer unit circuit to a transfer unit circuit subsequent to the next transfer unit circuit.